RSDS (Reduced Swing Differential Signaling) or mini-LVDS (Low Voltage Differential Signaling) may be used in an interface between a timing controller and a source driver for a display panel. However, these two methods require quite a lot of lines, with differing high frequency operations.
FIG. 1 is a waveform of a related transmitting signal. To solve above disadvantages, as shown in FIG. 1, a clock signal (CLK) may be embedded in a multi-level signal to reduce signal lines, and AiPi (Advanced Intra Panel Interface) enabling high frequency operation, may be used. However, such AiPi has the following disadvantages with respect to signal restoration.
First of all, the usage of the multi-level signal may increase electricity consumption in comparison to usage of a single level signal, thereby also increasing EMI (Electromagnetic interference). Secondly, an additional reference signal (Vrefh, Vrefl) line is necessary to restore the clock signal. Thirdly, if a level of the reference signal changes, that is, there is change in a data signal or out of the clock signal, the clock signal would be restored incorrectly or not corrected at all. The reference signal is changed easily by changes of a process or a power, voltage, or temperature. Fourthly, a difference between the clock signal and the data signal results in a difference in the transition time. This difference will make both of the clock and data signals restored from the receiver terminal fail to synchronize. As a result, a problem might occur in a timing margin for latching the data signal.